Presently, memory testing at integrated circuit level is usually handled in one of two ways. For relatively small memories (say, about 500 bytes or less), existing scan chains can be used. For example, referring to FIG. 1, data is fed serially into stimulus scan cells 10 until they contain the desired input values. The output of the stimulus scan cells 10 is then clocked into a memory location within memory block 11. The memory location is read out into response scan cells 12, and the output is compared with that the original input. This can be done using, for example, a comparator (not shown).
There are a number of standard test data sequences that are used within field of memory testing. These tests are called Marinescu XN tests, where X represents the number of read/write operations per memory location. For example, a 6N test is defined by the following sequence:w1(up) r1w0(up) r0w1r1(down)where:                w=write        r=read        (up)=increment the present memory column address        (down)=decrement the present memory column address        
Similarly, a 17N test is defined by the following sequence:w0(up) r0w1w0w1(up) r1w0r0w1(up) r1w0w1w0(down) r0w1r1w0(down)
Other test sequences exist and can be used depending upon the particular needs of the memory being tested.
An advantage of testing using existing cells is that it avoids the need for additional circuitry. Also, because the data is fed in via scan cells, such testing is relatively flexible, and can be changed at any time with suitable programming. However, using scan chains is also a relatively slow process, because data must be serially input and output from the scan cells prior to being clocked into memory.
For larger memories, the preferred choice for testing is to provide a Built In Self Test (“BIST”). Referring to FIG. 2, the BIST arrangement includes a BIST stimulus generator 20, the output of which is fed into one input of a multiplexor 21. The output of the stimulus scan cells 10 is fed into the other input of the multiplexor 21. The output of the multiplexor 21 is connected to the memory block 11, the output of which is supplied to a demultiplexor 22, which selectively outputs to either a BIST response capture unit 23 or the response scan cells 12.
The multiplexor 21 and the demultiplexor 22 are controlled to toggle the arrangement between a test mode, in which the BIST components interface with the memory block, and an operational mode, in which the scan chains interface directly with the memory block. For clarity, control and timing lines to the various components have been omitted.
One disadvantage with the BIST arrangement is that the stimulus generator is hard coded with a single testing scheme, and this cannot be changed without making fundamental changes in silicon. Moreover, when adding BIST functionality, the various lines used for controlling operation of the BIST components must all be manually routed during the design phase. This increases the chance of human error, which can result in costly redesigns or the production of integrated circuitry that cannot be tested properly.
It would be desirable to provide an arrangement that offers some of the desirable aspects of scan chain testing without the relatively long test times.